With the Compute Express Link, the CXL Consortium has created a low-latency and cache-coherent high-speed interconnect for systems that connects internal system components such as memory expansions and auxiliary processors to the host CPUs. Via it, CPUs are supposed to exchange their data with GPUs, DPUs (Data Processing Unit), TPUs (Tensor Processing Unit), SmartNICs or FPGAs as well as with memory buffers and other additional memory. For this purpose, CXL uses PCIe 5.0 as an interface, the specification of which was completed in 2019 and for which the first components are already available.
PCIe 5.0 is full-duplex capable and works with 3938 MByte per second, lane and direction, the PCIe 6.0 which is in the development phase with 7529 MByte / s. In this way, CXL should benefit from the further development of the system bus. The three protocols CXL.io, CXL.cache and CXL.memory are an in-house development of the CXL consortium. They take care of the three core components that are important for low-latency transmission: I / O, communication with the memory and cache coherence. CXL thus supplements the I / O semantics of the PCIe protocol with coherence and memory semantics, which are increasingly coming to the fore through the use of accelerators and SmartNICs.
The CXL Consortium is an open association of IT companies founded in 2019 with the goal of developing technical specifications to increase system performance and thus an open ecosystem for high-speed applications. The founding members included Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, Intel and Microsoft. Meanwhile representatives from AMD, ARM, IBM, Microchip, Nvidia and Xilinx sit on the board of directors; the consortium has a total of over 150 members.
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